syntax highlighting on blog

since syntax highlighter doesn't support vhdl and verilog code yet, so i manually convert the highlighted text file into html file. following the steps:

• open your code using kwrite and set the highlighting color as your flavor by selecting "Settings > Configure Editor..." and clicking on "Fonts & Colors"
  

• export your code into html file by clicking on "File > Export as HTML..." and "Save"

• copy the html source of your html file by opening your html file with your internet browser and clicking on "View > Page Source" (if you are using mozilla firefox). copy from tag <pre> to </pre>.
  

• paste it into your new posting blog in side "Edit Html" tab box and click back on "Compose" tab box to see the result.
  

• add border to make it beautiful by changing html tag <pre> with following settings.
  

<pre style="border: 1px dashed rgb(64, 64, 64); margin: 0em; padding: 1em; overflow: auto; background-color: rgb(0, 0, 0);">

• done! following examples of highlighted vhdl and verilog code
  

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Const_Unit is
   Port (Imm : in std_logic_vector(15 downto 0);
         CS : in std_logic;
         Const : out std_logic_vector(31 downto 0));
end Const_Unit;

architecture Behavioral of Const_Unit is
begin
   -- pass the 16 lsb value.
   Const(15 downto 0) <= Imm(15 downto 0);

   process (CS, Imm) begin
      if (CS = '0') then
         -- unsign value
         Const(31 downto 16) <= X"0000";
      else
         -- sign value (sign extension)
         for i in 31 downto 16 loop
            Const(i) <= Imm(15);
         end loop;
      end if;
   end process;
end Behavioral;

code: highlighted vhdl code

`timescale 1ns / 1ns

`include "../inc/ctr.h"

module ctr(
   // input
   clk, rst,
   // output
   out
);
   // i/os
   input                      clk,        // clock
                              rst;        // reset
   output [`WIDTH-1:0]        out;        // output
   // internal signals
   wire                       clk,        // clock
                              rst;        // reset
   reg    [`WIDTH-1:0]        out;        // output

   always @(posedge clk or posedge rst) begin
      if (rst)
         out <= 0;
      else
         out <= out + 1;
   end

endmodule

code: highlighted verilog code

opensparc for hobby (setting ide)

the first time i knew and directly downloaded opensparc source code was eight months ago. i grab it just for hobby so i don't have any plan to buy any expensive ide, simulator, synthesizer, or loader. i don't even want to put it into a die. i want to grab it using open source or free software and load it (part of it) into an fpga board.

what did i do so far are:

• joining related project

i join opensparc-t1 s1 project and fpga project.

• finding open source software

i'm currently using debian gnu/linux 4.0 for the operating system, eclipse 3.3.1.1 and verilog editor 0.5.2 for the ide, icarus verilog 0.8 for the simulator, gtkwave 1.3.81 for the waveform viewer of the simulation result. for the synthesizer, i have tried s1 core using icarus verilog but it fail.

eclipse ide for verilog editor on debian gnu/linux 4.0

i have added opensparct1.1.5 and s1 core as eclipse project. i also set the eclipse to automatically run some external tools for s1 project to build icarus simulation, run icarus simulation, and display test waveform.

in the following example, i extract the s1 core under .../openSparc/s1_core/ directory.

following steps show you how to set the external tools to build icarus simulation:
+ select run - external tools - open external tools dialog...
+ on the left box, double click program
+ on the right box, fill in:
___- name: s1 - build icarus simulation
+ on main tab, fill in:
___- location: .../openSparc/s1_core/tools/bin/build_icarus
_____(location of build_icarus script)
___- working directory: ${workspace_loc:/s1_core}
_____(s1 core working directory)
+ on environment tab:
___- click on new... button
___- fill in variable name with FILELIST_ICARUS, value with .../openSparc/s1_core/hdl/filelist.icarus
_____(location to filelist.icarus file)
___- click on new... button again
___- fill in variable name with S1_ROOT, value with .../openSparc/s1_core
_____(location to filelist.icarus file)
+ please make sure that the directories and environment variables are correct. one mistake can destroy your data. it because the s1 script execute "rm -rf *" command.
+ click on apply and close button
+ the new setting will appear at run - external tools - s1 - build icarus simulation

following steps show you how to set the external tools to run icarus simulation:
+ select run - external tools - open external tools dialog...
+ on the left box, double click on program
+ on the right box, fill in:
___- name: s1 - run icarus simulation
+ on main tab, fill in:
___- location: .../openSparc/s1_core/tools/bin/run_icarus
_____(location to run_icarus script)
___- working directory: ${workspace_loc:/s1_core}
_____(s1 core working directory)
+ on environment tab:
___- click on new... button
___- fill in variable name with S1_ROOT, value with .../openSparc/s1_core
_____(location to filelist.icarus file)
+ click on apply and close button
+ the new setting will appear at run - external tools - s1 - run icarus simulation

following steps show you how to set the external tools to display test waveform:
+ select run - external tools - open external tools dialog...
+ on the left box, double click on program
+ on the right box, fill in:
___- name: s1 - display test waveform
+ on main tab, fill in:
___- location: /usr/bin/gtkwave
_____(location of gtkwave application)
___- working directory: ${workspace_loc:/s1_core}
_____(s1 core working directory)
___- arguments: run/sim/icarus/trace.vcd tools/src/gtkwave.sav
+ on environment tab:
___- click on new... button
___- fill in variable name with S1_ROOT, value with .../openSparc/s1_core
_____(location to filelist.icarus file)
+ click on apply and close button
+ the new setting will appear at run - external tools - s1 - display test waveform

the default font setting form eclipse is too big for me, so i change it from window - preferences... than select general - appearance - colors and fonts. some other gtk default font can be changed also. read this blog on how to make eclipse look good on linux.

• finding free software

i have installed xilinx ise webpack 9.2i on my debian gnu/linux 4.0 box. i need only to install a new library and it just work. as the default, debian comes with libstdc++6, but xilinx ise webpack 9.2i requires libstdc++5. just install the old library without removing the new one.

the synthesis works fine but you can't find any fpga board that is supported by xilinx ise webpack edition that can feed opensparc t1or even s1 core in. the default simulator (just a simple simulator) form xilinx ise webpack also can't simulate s1 core test.

xilinx ise webpack on debian gnu/linux 4.0